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JChoi2's avatar
JChoi2
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6 years ago

Does tx_outclock of ALTLVDS_TX have to be connected to dedicated clock output pin?

I use Stratix V/ Arria10 Device. I made serdes with ALTLVDS_TX. I want output tx_outclock of ​ALTLVDS_TX to pin. Does tx_outclock of ALTLVDS_TX have to be connected to dedicated clock output pin?...
JChoi2's avatar
JChoi2
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6 years ago

​Thank you HPB

>As tx_outclock generated from a PLL,

In my case, the outclock divide factor is 2,

then tx_outclock is generated from serdes, the tx_in of serdes is "10101010.."

tx_outclock is one of the serialized data output port of channel.

In this case also, dedicated clock output has better jitter than regular I/o?

Regards

JC

  • HBhat2's avatar
    HBhat2
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    6 years ago

    Hi,

    TX_outcock is generated by internal PLL itself by taking inclock as the input. The PLL itself divides the reference clock to required frequency and outputs at tx_outclock port. So, in my view, it is better to connect to "PLL_xx_CLKOUT" pin of same bank where tx_out is placed.

    With regards,

    HPB