Forum Discussion
Altera_Forum
Honored Contributor
10 years agoI think the vhdl I have is much the same as that referred to by the wiki page.
Certainly my avalon slave does much the same as the referenced code. I have a bit of nasty logic to divide the Avalon clock down by a factor of 4 (from 62.5MHz to just over 15) but I don't think that is causing grief. (It uses the falling edge to generate a mask for the clock, so removes three of every 4 clock pulses.)