Forum Discussion

New Contributor

5 years ago

Solved

Does Cyclone 10 GX general-purpose IO SERDES support diff SSTL-12 output?

In the post

https://community.intel.com/t5/Intel-High-Level-Design/Cyclone10-GX-SERDES-using/m-p/1289577/emcs_t/S2h8ZW1haWx8dG9waWNfc3Vic2NyaXB0aW9ufEtQV0Y3OTBZN0I0T1NafDEyODk1Nzd8U1VCU0NSSVBUSU9OU3xoSw#M1830,

it is stated that

"When using dedicated SERDES circuitry, it does not support differential SSTL IO standard. The SERDES requires a direct connection to I/O and hence it can only interface to true LVDS I/O. So, please change IO standard of TX pins to LVDS."

This statement conflicts with table 52 of Intel Cyclone 10 GX Core Fabric and General Purpose I/Os Handbook (https://www.intel.com/content/www/us/en/programmable/documentation/vua1487061384661.html), which explicitly states that SERDES Transmitter I/O Standards Supports diff SSTL-12 (please see the follow screenshot).

Could you please clarify?

AminT_Intel
5 years ago
Hello,

The maximum achievable I/O frequency is different for each I/O standard and is depends on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.

Thank you

4 Replies

AminT_Intel
Regular Contributor
5 years ago
Hello,

1) The IP is for LVDS only. The name itself is LVDS SERDES Intel FPGA IP. So it supports only LVDS.

2) The restriction arises because it mentions that it requires true differential I/O standard. Only LVDS support that

3) Section 5.6.3 does not say about the dedicated circuitry.

Thank you.
- Twincreeks
  New Contributor
  5 years ago
  Thank you for your reply.
  
  As you said, the LVDS SERDES IP supports only LVDS. How does Cyclone 10 GX general-purpose support 1.434 Gbps differential SSTL-12 (https://community.intel.com/t5/Programmable-Devices/Does-Cyclone-10-GX-general-purpose-support-1-434-Gbps/m-p/1287593)? I need to transmit 1.434 Gbps data in diff SSTL-12. I cannot use LVDS because the common mode voltage of LVDS is not compatible with the data receiver.
  - AminT_Intel
    Regular Contributor
    5 years ago
    Hello,
    
    The maximum achievable I/O frequency is different for each I/O standard and is depends on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.
    
    Thank you

Forum Discussion

Does Cyclone 10 GX general-purpose IO SERDES support diff SSTL-12 output?

4 Replies

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