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Twincreeks's avatar
Twincreeks
Icon for New Contributor rankNew Contributor
4 years ago
Solved

Does Cyclone 10 GX general-purpose IO SERDES support diff SSTL-12 output?

In the post https://community.intel.com/t5/Intel-High-Level-Design/Cyclone10-GX-SERDES-using/m-p/1289577/emcs_t/S2h8ZW1haWx8dG9waWNfc3Vic2NyaXB0aW9ufEtQV0Y3OTBZN0I0T1NafDEyODk1Nzd8U1VCU0NSSVBUSU9O...
  • AminT_Intel's avatar
    AminT_Intel
    4 years ago

    Hello,

    The maximum achievable I/O frequency is different for each I/O standard and is depends on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.

    Thank you

AminT_Intel's avatar
AminT_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hello,

    • AminT_Intel's avatar
      AminT_Intel
      Icon for Regular Contributor rankRegular Contributor
      4 years ago

      Hello,

      The maximum achievable I/O frequency is different for each I/O standard and is depends on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.

      Thank you

      • AminT_Intel's avatar
        AminT_Intel
        Icon for Regular Contributor rankRegular Contributor
        4 years ago

        I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.