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It is possible to write a synchronizer chain to synchronize incoming asynchronous signals and prevent metastability. It shall be a few lines of code. Does Altera have a special megafunction to do this or atleast some guidelines so Quartus understands that we are trying to infer a synchronization chain?
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Make your own, it is not hard. Define a verilog module that has CLK, IN, and OUT ports, and internally does an N-rank pipeline delay synchronizer between IN and OUT based on CLK. Then you can instantiate this module however many times you want.
For extra credit you can add a parameter input that specifies the number of levels of delay you want (defaulting to two, for example) but allows you do parameterize the module, if needed.
And you could make the IN and OUT be programmable width, instead of just a default of one bit wide.
Honored Contributor
