Documentation for twentynm_iopll

Hi @roeekalinsky

We do not provide documentation on the WYSIWYG component twentynm_iopll.

You may checkout the IOPLL IP User Guide instead.

https://www.intel.com/content/www/us/en/programmable/documentation/mcn1403678389838.html

Best Regards,

Richard Tan

@RichardTanSY_Altera, thanks for the reply.

I'm already well acquainted with this document. I've been attempting to use the IOPLL IP, and finding that it's not working as expected per this document.

This document fails to explain what I'm seeing, and thus far so does this community forum (see: https://community.intel.com/t5/Programmable-Devices/Clock-synthesis-and-de-skewing-using-an-IOPLL-in-Arria-10/m-p/1294531 )

So there's the catch 22. The generated IP doesn't seem to be working right, and at the same time it obscures what's really going on underneath, which is making it impossible to debug. Hence the desire to gain better visibility into what's really happening at the WYSIWYG level.

If Altera can't/won't provide visibility at the WYSIWYG level, what else do you suggest?

Thanks,
-Roee

Thanks, @RichardTanSY_Altera.

Yes, I had already found the component declaration, but without documentation that's not particularly useful.

As to the IP, I've now obtained clarification on the IP's behavior that I was observing. The IP is reportedly operating per its design intent. The apparent discrepancy was a matter of misunderstanding / incorrect assumptions about the IOPLL's operating characteristics when its refclk input is fed by a GCLK, a supported topology but whose compensation characteristics were not explicitly specified in the documentation for the IP either.

A general plea to Intel/Altera, not only on this particular issue: Please make more comprehensive documentation available to us end users. It will save everyone a lot of time and headaches, and reduce Intel's customer support burden.

Thanks,
-Roee

Hi @roeekalinsky

Could you help to describe more on the misunderstanding about the IOPLL operating characteristics when its refclk input is fed by a GCLK?

Perhaps a screenshot may helps for understanding.

After that, I will feedback to the engineering based on your feedback so to update the document accordingly.

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.

Hi @RichardTanSY_Altera ,

I described it in greater detail in the other thread that I referred to earlier:

https://community.intel.com/t5/Programmable-Devices/Clock-synthesis-and-de-skewing-using-an-IOPLL-in-Arria-10/m-p/1297888/highlight/true#M80651

Please see my post of yesterday on that thread. If what I described there is not sufficiently clear, or if you'd like any more information on the issue, please let me know and I'll be happy to provide.

Thanks,

-Roee

Hi @roeekalinsky

I have spoke with the agent that taking care of your other case. The agent will help to communicate with the internal team in regards to the document not clear issue.

I believe I have answered the question in this case. With that, please allow me to transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.

Thanks, @RichardTanSY_Altera.

Yes, you've answered my question. Thanks. And thank you for passing this along to your internal team so they can hopefully improve the documentation.

Having a better understanding the limitations of the IOPLL, I've now achieved my design goals using a different approach. So as far as I'm concerned, we can close the thread.

Thanks again,
-Roee