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Altera_Forum's avatar
Altera_Forum
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15 years ago

Do I need external SRAM?

Dear experts,

I am considering using EP3C25 (Cyclone III) devices with Active Serial Configuration device (64Mbit EPCS64) with or without external SRAM.

My program file will be stored in EPCS64 and my EP3C25 will be booted from that devices.

Question:

1) Is there any option not to use external SRAM to support big program file (size greater than on-chip SRAM available)?

2) Is it possible to boot cyclone III directly from configuration device without loaded to any RAM?

(I am a beginner and still not really understand completely how Cyclone III will boot)

Thank you in advance.

Skw

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    SRAM is not required for booting any fpga device. Upon boot configuration data is transferred from epcs (or any other configuration device based on NV memory) in dedicated sram cells which store configuration in a volatile way; this sram is dedicated for configuration and is not available to user design.

    Everything else depends on what you are using the fpga for. If you configure a Nios processor you usually need external memory for storing instructions and data, but this is not strictly necessary.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    You will not be able to run code directly out of the EPCS device since there is a protocol involved instead of plain reads/writes. Long ago I saw someone post something in the old Nios forum that implemented this protocol. It would be very slow plus code doesn't access variables in flash block size sectors so leaving data that needs write access in the EPCS device probably wouldn't be a good idea/possible. If you can manage to find that component in here (it may have been copied over from the old forum) what you might be able to do is put the .text and .rodata sections into the EPCS device and put .rwdata, heap, and stack into on-chip memory.

    Since the EPCS link is serial expect fairly poor performance from the CPU if it performs a lot of memory accesses to it. Slapping a small x8 SDRAM onto the board would probably be a better idea in my opinion if you want to keep the pin count low. Using SDRAM in half-rate mode will bring the interface hooked up over Avalon-MM up to x32 and would match the CPU width giving fairly good results assuming you add some processor cache.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Cris72, BadOmen,

    Thank you for the answer.

    I forgot to mention that I will use Nios processor. EP3C25's onchip RAM (592Kbits) seems a bit too few. I think I will consider using external memory SSRAM.

    Thanks again:)

    Skw