dmx-512 vhdl/verilog code

this is for receiver unit of DMX-512 which used anly 6 channels and same data

-------------------------------------------------------------------------------

-- Entity for Receive Unit - 250K DMX baudrate --

-------------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

--library work;

-- use work.UART_Def.all;

-------------------------------------------------------------------------------

-- Receive unit

-------------------------------------------------------------------------------

entity RxUnit is

port (

Clk : in Std_Logic; -- system clock signal

Reset : in Std_Logic; -- Reset input

RxD : in Std_Logic; -- RS-232 data input

BREAK : out Std_Logic; -- Status signal

DataIn : out Std_Logic_Vector(7 downto 0);

BitStart: out Std_Logic);

end entity; --================== End of entity ==============================--

-------------------------------------------------------------------------------

-- Architecture for receive Unit

-------------------------------------------------------------------------------

architecture Behaviour of RxUnit is

-----------------------------------------------------------------------------

-- Signals

-----------------------------------------------------------------------------

signal Start : Std_Logic; -- Syncro signal

signal tmpRxD : Std_Logic; -- RxD buffer

signal BreakDetected : Std_Logic; --

signal BitCnt : Unsigned(3 downto 0); --

signal SampleCnt : Unsigned(3 downto 0); -- samples on one bit counter

signal ShtReg : Std_Logic_Vector(7 downto 0); --

signal DOut : Std_Logic_Vector(7 downto 0); --

begin

---------------------------------------------------------------------

-- Receiver process

---------------------------------------------------------------------

RcvProc : process(Clk,Reset,RxD)

variable tmpBitCnt : Integer range 0 to 15;

variable tmpSampleCnt : Integer range 0 to 15;

constant CntOne : Unsigned(3 downto 0):="0001";

begin

if Rising_Edge(Clk) then

--tmpBitCnt := ToInteger(BitCnt);

tmpBitCnt := To_Integer(BitCnt);

--tmpSampleCnt := ToInteger(SampleCnt);

tmpSampleCnt := To_Integer(SampleCnt);

if Reset = '0' then

BitCnt <= "0000";

SampleCnt <= "0000";

Start <= '0';

BreakDetected <= '0';

ShtReg <= "00000000"; --

DOut <= "00000000"; --

else

if Start = '0' then

if RxD = '0' then -- Start bit,

SampleCnt <= SampleCnt + CntOne;

Start <= '1';

BreakDetected <= '0'; -- clear output

end if;

else

if tmpSampleCnt = 8 then -- reads the RxD line

tmpRxD <= RxD;

--BitStart <= '1'; -- position marker for debugging

SampleCnt <= SampleCnt + CntOne;

elsif tmpSampleCnt = 15 then

--BitStart <= '0'; -- position marker for debugging

case tmpBitCnt is

when 0 => -- Waiting for start bit (should be '0')

if tmpRxD = '1' then -- Not detected.

Start <= '0';

--tmpDRdy <= '0';

else

BitCnt <= BitCnt + CntOne;

end if;

SampleCnt <= SampleCnt + CntOne;

when 1|2|3|4|5|6|7|8 =>

BitCnt <= BitCnt + CntOne;

SampleCnt <= SampleCnt + CntOne;

ShtReg <= tmpRxD & ShtReg(7 downto 1);

when 9 => --1st stop bit

if tmpRxD = '0' then -- Check for stop bit (should be '1')

-- Stop bit not detected. Either fault, or BREAK signal.

BreakDetected <= '1';

BitCnt <= BitCnt + CntOne; -- Goto state 10 and wait for stop

SampleCnt <= SampleCnt + CntOne;

else

-- Stop bit found so reset and wait for

-- next falling edge of start bit.

BreakDetected <= '0';

BitCnt <= "0000"; -- Goto state 00 and wait for start

SampleCnt <= "0000";

Start <= '0';

end if;

DOut <= ShtReg;

when 10 =>

-- Ensure RxD is high before continuing...

-- This caters for BREAK byte length (88uS with no stop bits)

if BreakDetected = '1' then -- we are waiting for a return to a high state

if tmpRxD = '1' then -- check for high state

-- High state detected, so abandon this and wait for the falling

-- edge of the next START bit.

BitCnt <= "0000";

SampleCnt <= "0000";

Start <= '0';

end if;

SampleCnt <= SampleCnt + CntOne;

end if;

when others =>

null;

end case;

else

SampleCnt <= SampleCnt + CntOne;

end if;

end if;

end if; -- if reset=...

end if; -- rising clock

end process;

DataIn <= DOut;

BREAK <= BreakDetected;

BitStart <= Start;

end Behaviour; --==================== End of architecture ===================

TX and th RX unit should combined den only v can run the code