DMA Speed Issues

Thanks Ted for your suggestion. I will try them out. How can I modify the Avalon slave to handle a burst read? Should I just trap the incrementing read address and output data from the FIFO which means my slave should have a larger address range?

Anish

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Your SignalTap didn't include the waitrequest, but I think the only thing you're seeing here is the universal truth that an external memory like SDRAM/DDR has a big performance hit when you read/write to it word-at-a-time. You need to burst to get anything reasonable performance-wise.

What you need is a non-bursting read from the FIFO constant address, and a bursting write to the SDRAM/DDR memory. I think you should be able to do this with the mSGDMA.

If the FIFO is embedded in an IP core of your creation, you could of course just modify your Avalon-MM to receive the burst read. Or using off-the-shelf blocks, you could also use mSGDMA Avalon-ST to Avalon-MM conversion.

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