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Jerome's avatar
Jerome
Icon for New Contributor rankNew Contributor
6 years ago
Solved

DMA freezing ?

Hi guys, I'm trying to make a simple design on my Intel Dev Kit MAX10 with the NIOS 2, DDR3 sdram controller and the DMA. I write directly a pattern into my memory (1Gb in 64Mb*16) via NIOS 2 and ...
  • Jerome's avatar
    Jerome
    6 years ago

    So,

    I've found my trouble...

    while(IORD_ALTERA_AVALON_DMA_STATUS(DMA_BASE) == 0x02); //If DMA transaction is in progress then wait
 
IOWR_ALTERA_AVALON_DMA_CONTROL(DMA_BASE, 0x0);
IOWR_ALTERA_AVALON_DMA_STATUS(DMA_BASE, 0x0);
 
IOWR_ALTERA_AVALON_DMA_RADDRESS(DMA_BASE,0x0); //specifies the first location to be read in a DMA transaction
 
IOWR_ALTERA_AVALON_DMA_WADDRESS(DMA_BASE,0x2); //specifies the first location to be written in a DMA transaction
 
IOWR_ALTERA_AVALON_DMA_LENGTH(DMA_BASE,2); //specifies length (in Bytes) of transfert
 
IOWR_ALTERA_AVALON_DMA_CONTROL(DMA_BASE, 0x038A); //WCON, RCON, LEEN, GO, HW to 1
 
while(IORD_ALTERA_AVALON_DMA_STATUS(DMA_BASE) == 0x02);
 
IOWR_ALTERA_AVALON_DMA_STATUS(DMA_BASE, 0x0);
IOWR_ALTERA_AVALON_DMA_CONTROL(DMA_BASE, 0x0);

    and then, was just pre-configuring control register before transaction...

    while(IORD_ALTERA_AVALON_DMA_STATUS(DMA_BASE) == 0x02); //If DMA transaction is in progress then wait
 
IOWR_ALTERA_AVALON_DMA_CONTROL(DMA_BASE, 0x0382);
IOWR_ALTERA_AVALON_DMA_STATUS(DMA_BASE, 0x0);
 
IOWR_ALTERA_AVALON_DMA_RADDRESS(DMA_BASE,0x0); //specifies the first location to be read in a DMA transaction
 
IOWR_ALTERA_AVALON_DMA_WADDRESS(DMA_BASE,0x2); //specifies the first location to be written in a DMA transaction
 
IOWR_ALTERA_AVALON_DMA_LENGTH(DMA_BASE,2); //specifies length (in Bytes) of transfert
 
IOWR_ALTERA_AVALON_DMA_CONTROL(DMA_BASE, 0x038A); //WCON, RCON, LEEN, GO, HW to 1
 
while(IORD_ALTERA_AVALON_DMA_STATUS(DMA_BASE) == 0x02);
 
IOWR_ALTERA_AVALON_DMA_STATUS(DMA_BASE, 0x0);
IOWR_ALTERA_AVALON_DMA_CONTROL(DMA_BASE, 0x0);
NurAida_A_Intel's avatar
NurAida_A_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Hi Sir,

You can refer to Chapter 3 (page 37) on this "UniPHY Design Tutorials" for Qsys (http://www.altera.com/literature/hb/external-memory/emi_tut_qdr.pdf). They have used DMA in the system. The design example targets the Stratix IV FPGA development kit which includes a 16-bit wide, 1-Gb Micron MT41J64M16LA-15E 667-MHz DDR3 SDRAM component but it is helpful to get an idea on how everything should works.

Hope this is helpful for you.

Thanks

Regards,

NAli1

Jerome's avatar
Jerome
Icon for New Contributor rankNew Contributor
6 years ago

Hi NALi1,

Thank you for your answer, that will be helpful I hope. I'm looking at the PDF. I'll be back soon if that's work ! :)

Best regards,

Jerome.