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Zaher's avatar
Zaher
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5 years ago

DMA Controller with external DREQ/DACK mechanism on CPLD or FPGA

Hello everyone, I've been working with microcontrollers for quite some time now. I have never used a CPLD or FPGA for any of the projects I worked on. I don't know why the idea seems intimidating f...
Hazlina_R_Intel's avatar
Hazlina_R_Intel
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5 years ago

This is the latest link for AN492: https://fpgacloud.intel.com/devstore/platform/16.0.0/Standard/compactflash-interface-an-492/?wapkw=an492


We have other design examples in our Design Store here: https://fpgacloud.intel.com/devstore/


For DMA controller IP you may refer to the brief here: https://www.intel.com/content/www/us/en/secure/design/internal/content-details.html?DocID=618538


On your question on the feasibility to use Nios II embedded processor IP core in addition to the IDE/ATA controller core and the DMA controller core in one single device without a microcontroller, let me get an engineer to assess this for you.


-Hazlina


Zaher's avatar
Zaher
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5 years ago

Thank you very much for the follow up. I have downloaded the material available for AN492 on the link you provided. I have been to the Design Store, but I didn't see any examples for ATA/IDE controller or CF card interfacing. If you are referring to examples for these particular applications, please provide links to those examples.

Unfortunately, I couldn't access the resource for the DMA controller IP on the link you provided. It has requested extra privileges and a CNDA. I made the request, but not sure whether or when it would be approved so I can access that resource.

It would be great if you can get some feedback from one of your engineers about the scenario I have in mind.

Regards,

Zaher