bluncan
New Contributor
1 year agoDK-SI-AGI027FA directphy_f not locking
Hello everyone,
I'm trying to bring-up a JESD204B project on a dk-si-agi027fa board but I'm facing some issues regarding the transceivers PLL. I am using FGT clocking, the input frequency of the IP (directphy_f) is set to 200 MHz but no matter the output frequency the tx_pll_locked or rx_is_lockedtodata signals are stuck at '0'. I'm feeding the clock through the J19 SMA port on the devboard and I've set the MUX_SEL0 signal to '1'. There are no weird warnings during the compilation or implementation.
Do I need to do something from software in order for the PLL to lock or what might cause this issue?
Thank you for your help!
Regards,
Bogdan