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bluncan's avatar
bluncan
Icon for New Contributor rankNew Contributor
2 years ago

DK-SI-AGI027FA directphy_f not locking

Hello everyone, I'm trying to bring-up a JESD204B project on a dk-si-agi027fa board but I'm facing some issues regarding the transceivers PLL. I am using FGT clocking, the input frequency of the IP ...
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Ash_R_Altera's avatar
Ash_R_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi,

For starter, can you try to change the MUX_SEL0 = '0' and configure the directphy clock frequency to the 100 MHz coming from U22 on board. Another check will be to verify the refclock input configured in the SYSPLL IP. It should be refclock 0.


Regards