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Altera_Forum
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15 years ago

Dividing two N-bit signed binary (with fractional bits) in Quartus

In my design, I am required to divide a signed 16-bit binary, say A, with another signed 16-bit binary, say d. Both inputs have decimal and fractional bits.

The denominator d is actually a positive number and always less than or equal to 1; so it's basically fractional majority of the times. Now since division uses up a lot of resources, I am thinking of simply multiplying 1/d by A.

For this, I was looking at using the lpm_mult megafunction, with input datab as a constant. Unfortunately, the megafunction only takes in integers as constants.

The output A/d should be also be a 16-bit signed binary (will have both decimal and fractional bits with sign).

Can you please suggest me other implementation possibilities, to either divide by d or multiply by 1/d?

Appreciate your guidance and help.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    You are on right track. you only need to scale 1/d by some power of 2 then truncate final result equally. e.g. .999 = .999 x 2^14/2^14

    hence scale .999 to = .999 * 2^14 = 16368

    In hardware truncate off 14 LSBs thus you get .999 in effect

    The real issue is how to get 1/d from d if not constant(may be lut...)
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    If 'd' has too much of a range and doesn't fit reasonably into a lookup table you may want to try serial division. A serial divider works on a single bit of the numerator per clock cycle so the calculation time is determined by the numerator width. So it doesn't have the pipelining performance of say lpm_divide that can handle a calculation after every clock cycle once the pipeline is warmed up but it's fairly small and hits a relatively high Fmax. I don't know if I have my implementation of it around still but it's a pretty easy thing to implement since it's based on the same techniques as you learned long ago in school called long division.

    Here is a link that shows how it is implemented in "C2H friendly" C code:

    http://www.altera.com/literature/hb/nios2/edh_c2h_optimization_design_files.zip

    It's easier to implement in verilog or VHDL so don't let the macro madness in the .zip file scare you :)