Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Disable Device ID check during JTAG Programming

Hello Community, Altera, Intel, sorry for multiple posts, but i would like to seperate discussions about 125°C Flash Memory. I would like to use a 125° Automotive configuration flash IC (...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

I worked through serial flash datasheets and think, I've found why the Macronix and Cypress devices fail in configuration phase although they could be correctly programmed and verified as reported by gj_leeson.

These chips have non-volatile enable bits for quad SPI mode that must be set once for ASx4 to be operational. Programming and verification by SFL uses single SPI mode, so the problem shows only during FPGA configuration. Micron N25Q256A (the original EPCQ256 chip) and MT25QL256 don't have a quad enable bit.

The best solution would be to write a modified Factory SFL application that sets the quad enable bits for the respective chips. If boot time isn't critical you might try ASx1 mode in programming file conversion.