Forum Discussion
Honored ContributorDirect Digital Synthesis
Dear Friends,
Can anyone suggest on how to implement DDS using ALtera Products. I have attached a PPT downloaded from a website for quick reference. Thanks in Advance21 Replies
Altera_ForumKaz,
There are some pretty cool DACs from TI that contain interpolating filters, etc., eg. check out the DAC3484. http://focus.ti.com/docs/prod/folders/print/dac3484.html Analog devices range of TxDACs has similar features; http://www.analog.com/en/digital-to-analog-converters/da-converters/ad9146/products/product.html As far as DDS devices go, I use the AD9956 AgileRF for generation of 1GHz ADC signals, with the DDS in the feedback path as a programmable divider and phase-shifter: http://www.analog.com/en/rfif-components/direct-digital-synthesis-dds/ad9956/products/product.html and the PLL/DDS circuit I use is here; http://www.ovro.caltech.edu/~dwh/carma_board/gda06rb004_carma_v0.87_dec03.pdf (http://www.ovro.caltech.edu/%7edwh/carma_board/gda06rb004_carma_v0.87_dec03.pdf) on page 88. The PLL/DDS design is documented here http://www.ovro.caltech.edu/~dwh/carma_board/ad9956_tests.pdf (http://www.ovro.caltech.edu/%7edwh/carma_board/ad9956_tests.pdf) If the original poster could explain what he really wants, I could tell if some of this material could help. Cheers, Dave- Altera_Forum
Interpolation externally (in DAC devices) is an expensive option and in that case I would rather use commercial DDS device. But I can think of using fpga multiple serdes channels to allow a sampling frequency > 1 G and hence one may get some 6 or 8 or more samples per cycle to be passed to a basic DAC device.
- Altera_Forum
That is not an issue caused by FPGAs. There are several causes for spectral purity.
Increase of nyquist frequency can be solved by using interpolating DACs and even FPGAs can be used to drive them. But this is not something which belongs to the original question. - Altera_Forum
I don't see fpga generating good quality sinusoid at 200MHz. This frequency if sampled at 400Mhz will have only two samples per cycle(+1,-1)
with harmonic problems. - Altera_Forum--- Quote Start --- I am looking at generating a frequency of 200 MHz and for a suitable DAC to work on the analog domain. will Cyclone clock at this frequency or more. --- Quote End --- You still have not provided enough information. Please explain what you would like to do with this signal? Its not clear that you even need to use an FPGA. If you just want a sinusoidal frequency, or I/Q tones, then you might be better off looking at Analog Devices DDS devices. So if you can explain what you are trying to do, I can help point you in the right direction. Cheers, Dave
- Altera_Forum
I am looking at generating a frequency of 200 MHz and for a suitable DAC to work on the analog domain. will Cyclone clock at this frequency or more.
Thanks - Altera_Forum
What are the requirements for the DDS (spurious free dynamic range, tuning frequencies, etc)? Do you plan on using it in the digital domain, or do you plan on driving an external DAC for use in the analog domain? Have you looked at external DDS devices? What other functionality do you require?
Cheers, Dave - Altera_Forum
Hi,
You can easily do that on a low cost device such as a Cyclone III, for example a 3C10 or even a 3C5 should fit - Altera_Forum
Thanks for your reply,
Pl reply Which FPGA is most suitable for prototyping the DDS. I assume that Stratix will be a good starter. With Kind Regards, S.Saravanan - Altera_Forum
Or build one by yourself.. this is not too complex. Just use a piece of memory blocks to store a quarter wave sine table, some logic for quadrant mapping and phase and frequency accumulator.
