Digitally Controlled Potentiometer DCP Altera DE0 Verilog HDL ISL23415

Hello everybody.

I am using the Altera DE0 Board and Verilog HDL to write on the ISL23415. The ISL23415 is a digitally controlled Potentiometer.

The 8 switches on the board are used to get an input. Next step is to convert the parallel input into serial output. No problem so far.

The MSB of the shifted values is connected to the SDI of the IC.

Unfortunatley i dont get any data in the chip. I guess there is some timing-problem.

To control my circuit i am measuring the resistance between ground and the pin 6 (RW) of the ISL23415.

Here is the data sheet: http://www.intersil.com/content/dam/intersil/documents/isl2/isl23415.pdf

Basically all you have to know:

• sdo is not necessary for the write sequence

• sdi receives operation code, wiper adress and data

• data is shifted in at posedge of sck, while cs is low

• write sequence is a two or more byte operation

• host (master) sends a valid Instruction byte. If the

module dcp (sck, sdi_reg, csu5, clk_50, switch, sdi, sdo); 
//sck = serial bus clock input
//sdo = serial bus data output -> not needed in the write sequence
//sdi_reg = serial bus data input
//csu5 = active low chip select
//Declaration of outputs, inputs and variables
input clk_50, sdo;
input wire  switch;
output sck, csu5;
output reg  sdi_reg;
reg  instr_reg; 
//output wire sdi;
output reg sdi;
        
reg  div_dcp;                    // 10 Hz 
reg  write_cntr;                    // 5 bit counter for the write sequence
//****************************************************************
// Write Sequence
// parallel to serial conversion
// data bits are shifted at the rising edge of sck and when CS is low
always @(posedge sck)                            
begin
    if(csu5 == 1)    
        begin
            sdi_reg <= switch;                        // data bytes        
            instr_reg <= 8'b11011111;                // If the  bits are zero or one, then the write is to the WRi register -> Instruction Byte            
        end                                                
    else if(write_cntr) sdi_reg <= sdi_reg;            // shift data byte
    else if(~write_cntr) instr_reg <= instr_reg;        // shift instruction byte
end
// send the shifted data to pin SDI
always @(posedge sck)
begin
    if(write_cntr == 1)
        sdi <= sdi_reg;
    else if(~write_cntr)
        sdi <= instr_reg;
end
//****************************************************************
// FPGA clock divider
always @(posedge clk_50)                                // clock divider, FPGA clock needs to be connected to DCP clock sck
begin                                                // counter for clockdivision of FPGA clock
    div_dcp <= div_dcp + 1;
end
//****************************************************************
//4 bit counter for dcp
always @(negedge sck)
begin
    write_cntr <= write_cntr + 1;
end
//****************************************************************
assign sck = div_dcp;                                   // sck is assigned to divided FPGA clock
assign csu5 = write_cntr;
                            
endmodule

Thank you for any advice ;)