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Honored ContributorDigital clock using verilog HDL
Hi,
I need to design a clock using 7 segment with stop watch and alarm in Verilog HDL language. As I am new in these HDL I can not find any solution. Can anyone help me to do that? Eraesh12 Replies
Altera_Forumhello. i am browsing over the net and i found this thread. i am a student and i am studying FPGA. we were asked to make a digital clock with alarm. i already have an idea how to do it. my problem is i don't know how to start. we were taught basic codes in school but we don't know how to make a program dealing with a clock. please help me. thank you. :)
- Altera_Forum
Hi Eraesh,
Personally I will encourage you to try and face it yourself as it is in your interest but I can suggest these guide lines. First forget about HDL coding but focus on how to do your design. You will need a suitable reference clock. run a counter on this clock and generate pulses for seconds/min/hrs then counters for seconds/minutes/hours that overflow as appropriate e.g. "seconds" counter running from 0 to 59 ...etc. design an algorithm for stop watch and a detection algorithm for alarm based n above three counters. once you get your counting ready, you need to display them. One way is to convert them from binary to BCD then decode that for the 7 segment display. Of course you need to consider refresh rate for display and define your inputs, these may include reset,ref clk,user inputs for time-setting or alarm-settings or stop-watch...your outputs will be the decoded values for say 8 display digits such as 00:00:00 as well as the alarm beep... Hope this helps Regards Kaz
