Hi, I need to design a clock using 7 segment with stop watch and alarm in Verilog HDL language. As I am new in these HDL I can not find any solution. Can anyone help me to do that? Eraesh

Hi Eraesh, Personally I will encourage you to try and face it yourself as it is in your interest but I can suggest these guide lines. First forget about HDL coding but focus on how to do your design. You will need a suitable reference clock. run a counter on this clock and generate pulses for seconds/min/hrs then counters for seconds/minutes/hours that overflow as appropriate e.g. "seconds" counter running from 0 to 59 ...etc. design an algorithm for stop watch and a detection algorithm for alarm based n above three counters. once you get your counting ready, you need to display them. One way is to convert them from binary to BCD then decode that for the 7 segment display. Of course you need to consider refresh rate for display and define your inputs, these may include reset,ref clk,user inputs for time-setting or alarm-settings or stop-watch...your outputs will be the decoded values for say 8 display digits such as 00:00:00 as well as the alarm beep... Hope this helps Regards Kaz

hello. i am browsing over the net and i found this thread. i am a student and i am studying FPGA. we were asked to make a digital clock with alarm. i already have an idea how to do it. my problem is i don't know how to start. we were taught basic codes in school but we don't know how to make a program dealing with a clock. please help me. thank you. :)

Did you even read kaz' answer? He gave tips on how to start. Now if you have a question on a more specific point, we can answer.

oh, i'm sorry. my problem is i don't know how to separate digital display 1-4 from each other. i can make counter counting from 0000 to 9999 but i don't know how to make it 00:59. also, if it reaches 00:59, how can i make it 01:00.? we have to display hh:mm and mm:ss when we use the dip switches. thank you for responding. :)

You should handle each digit separately. Have the first digit count from 0 to 9. When you need to go over 9, put it back to 0 and increase the second digit. When that second digit is at 5 and you need to increase it again, put it back to 0 and increase the third digit, etc.

Digital clock using verilog HDL | Altera Community

12 Replies

Altera_Forum
Honored Contributor
14 years ago
Nani..If i were you, I would have first got into understanding how numbers are represented using the 7-segment. Decimal to 7-segment conversion.
You might need to go through the hardware details for 7-segment displays on your board to understand if they are active HIGH/LOW (i.e. need to find if it is 0 or a 1 that activates each segment).

If you get this part, then you got very little to do further. Just maybe a check to see if you have reached a 9 so that you could start counting the next display. It is simpler than you would think.

Also a good reference would be the 7-segment code available in the TRDB-D5M sample project available on Altera website. Hope it helps!

Regards BP..
Altera_Forum
Honored Contributor
13 years ago
Here, check this out.It is working and downloadable onto fpga.
http://www.youtube.com/watch?v=c8v1nfz1zn8

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Digital clock using verilog HDL

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