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Altera_Forum
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17 years ago

Digital clock using verilog HDL

Hi, I need to design a clock using 7 segment with stop watch and alarm in Verilog HDL language. As I am new in these HDL I can not find any solution. Can anyone help me to do that? Eraesh
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Altera_Forum
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14 years ago

Nani..If i were you, I would have first got into understanding how numbers are represented using the 7-segment. Decimal to 7-segment conversion.

You might need to go through the hardware details for 7-segment displays on your board to understand if they are active HIGH/LOW (i.e. need to find if it is 0 or a 1 that activates each segment).

If you get this part, then you got very little to do further. Just maybe a check to see if you have reached a 9 so that you could start counting the next display. It is simpler than you would think.

Also a good reference would be the 7-segment code available in the TRDB-D5M sample project available on Altera website. Hope it helps!

Regards BP..