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Altera_Forum
Honored Contributor
17 years agoDigital clock using verilog HDL
Hi, I need to design a clock using 7 segment with stop watch and alarm in Verilog HDL language. As I am new in these HDL I can not find any solution. Can anyone help me to do that? Eraesh
Altera_Forum
Honored Contributor
14 years agoHere, check this out.It is working and downloadable onto fpga.
http://www.youtube.com/watch?v=c8v1nfz1zn8