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TBake8
New Contributor
New ContributorDifficulty setting pin Impedance
I'm trying to learn how to implement a 3V LVTTL interface using a Cyclone IV E (EP4CE10) FPGA. However, I would like to ensure that the input/output impedances of the IO is at 50R. I see that it is p...
Rahul_S_Intel1
Frequent Contributor
Frequent ContributorHi,
From the above I can assume that the impedance that is been briefed is about the OCT . The Table 6-2 give you the setting for the OCT ( page no: 7)
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-iv/cyiv-51006.pdf
Kindly follow the table .
