Differential clock buffer

Dear Nagakiran,

If you setup the pins with the correct differential IO standards and use the positive pole in your logic the fitter should be able to infer the negative pole of the differential input. You would then just need an assignment for your clock in your design to be a global clock to be promoted to the GCLK network.

For your output PLL clock, once against just make sure your pin out standard is correct and supply the clock as a dedicated single-ended output from a PLL. The fitter should map the PLL output to the correct dedicated PLL outputs, assuming the output pins you are driving are the dedicated output pins for a PLL. If they aren't the fitter can't ensure clock jitter performance since its based on routing. If you want to explicitly instantiate a differential buffer, you may be looking for an ALTIOBUF ?

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Hi,

I have an 100 MHz differential clock input to the Arria V FPGA. I need this clock to be the global clock. The ALTCLKCTRL IP contains the global clock buffer but I am not sure if this works in differential mode (there are no differential line inputs for this buffer). Can anyone please help me out?

Also I need to output PLL clock (different freq) as an output clock again as a differential clock (even here there are no differential lines for external clock buffer). What differential clock buffer do I need to use for this?

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Inside the Quartus II design, you would only see single line even for differential signal. The differential signaling is generally at the IO portion. Inside the FPGA, the signal is single ended. You would only need to assign your input/output pin with differential IO standard and placed them to differential pins.

Dear rgk, bfkstimchan,

Thanks for the reply.