Differential clock buffer

Dear Nagakiran,

If you setup the pins with the correct differential IO standards and use the positive pole in your logic the fitter should be able to infer the negative pole of the differential input. You would then just need an assignment for your clock in your design to be a global clock to be promoted to the GCLK network.

For your output PLL clock, once against just make sure your pin out standard is correct and supply the clock as a dedicated single-ended output from a PLL. The fitter should map the PLL output to the correct dedicated PLL outputs, assuming the output pins you are driving are the dedicated output pins for a PLL. If they aren't the fitter can't ensure clock jitter performance since its based on routing. If you want to explicitly instantiate a differential buffer, you may be looking for an ALTIOBUF ?