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Hi,
I have an 100 MHz differential clock input to the Arria V FPGA. I need this clock to be the global clock. The ALTCLKCTRL IP contains the global clock buffer but I am not sure if this works in differential mode (there are no differential line inputs for this buffer). Can anyone please help me out?
Also I need to output PLL clock (different freq) as an output clock again as a differential clock (even here there are no differential lines for external clock buffer). What differential clock buffer do I need to use for this?
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Inside the Quartus II design, you would only see single line even for differential signal. The differential signaling is generally at the IO portion. Inside the FPGA, the signal is single ended. You would only need to assign your input/output pin with differential IO standard and placed them to differential pins.
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