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Niko3's avatar
Niko3
Icon for Occasional Contributor rankOccasional Contributor
1 year ago
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different clock handling in simulation and real CPLD --> error: its ok

Hi, I believed to have found a difference between simulation and real chip behaviour. It was a mistake of mine. sorry 😉 This post can be deleted.
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Programmable Logic Device
  • TingJiangT_Intel's avatar
    TingJiangT_Intel
    1 year ago

    I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


TingJiangT_Intel's avatar
TingJiangT_Intel
Icon for Contributor rankContributor
1 year ago

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.