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So basically if I chose to generate test-bench qsys system and test-bench simulation model, the tool would generate a wrapper system containing an instance of DUT and another instance of BFMs
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Right, but the caveat is that the BFMs are attached to the "external" interfaces of the Qsys system, whereas most times you would want an Avalon-MM master BFM as part of the Qsys system, otherwise how can you exercise your system?
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however if I did your way, DUT and BFMs would be within a single instance (BFMs are now virtually a part of DUT), a simulation model of such a single instance is equivalent to the simulation model of the wrapper system right?
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Not quite. My method is a mixture. I add an Avalon-MM BFM to the Qsys system, so that I can read/write the Avalon-MM slaves at whatever addresses that BFM master is connected to (typically the same address map as another master), and then I create a testbench with an instance of the Qsys system, and then add BFMs manually to that testbench, eg., a DDR3 memory model.
For testing Avalon-MM slave I/Os, I just test the state of the signals in the testbench stimulus process, and don't bother with BFMs.
Cheers,
Dave
Honored Contributor
