Difference among Qsys Sim model, test-bench Qsys sys and test-bench Sim model

Your question is a little difficult to answer without knowing what sort of components you have added to your Qsys system.

Click on each of the options and look at the code generated.

Typically I just generate a simulation model (in VHDL or Verilog depending on what I am doing).

I then explicitly add BFMs or device models for testing.

For example, when testing Avalon-MM slave components, I explicitly add an Avalon-MM master BFM to the design, eg., take a look at this tutorial;

http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial

In this thread (post# 25)

http://www.alteraforum.com/forum/showthread.php?t=32952&page=3

I show how to use the master and slave BFM.

I've also used the Qsys "Example Design" to get an idea of how to connect the DDR3 controller to a DDR3 model, and then rather than using that code, re-written a testbench in the style that I like.

The key to understanding Qsys generated code is to read it as "example" code. If you do not like it, then its ok not to use it :)

Cheers,

Dave