DFF Clock Polarity & Other signal polarities

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Thanks pletz,

The document you linked is, I believe, a sub-section of the handbook ... which I downloaded and read a few days ago.

More specifically to my question, refer to the IO structure diagram on page 2-24 of the document you linked. As one can see, there's a great deal of configuration that can be specified for an IO point. Where I'm a bit confused is how these various settings are configured using schematic symbols.

For example, if you want to specify an open drain output, I believe you place a Primitives/Buffer/opndrn symbol before the pin. There are, however, many more options that I'm having trouble finding (or guessing) in the symbols library.

What I need is a cross-reference that correlates the desired I/O function to the relative symbol in the library. Does such a cross-reference exist ?

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Hi RWey,

the real I/O specification is not done in the schematic ( as far as I know). I/O standards, driver strength like other I/O features are logic option, which could be set in the assignment editor.

Kind regards

GPK

Thanks pletz,

The document you linked is, I believe, a sub-section of the handbook ... which I downloaded and read a few days ago.

More specifically to my question, refer to the IO structure diagram on page 2-24 of the document you linked. As one can see, there's a great deal of configuration that can be specified for an IO point. Where I'm a bit confused is how these various settings are configured using schematic symbols.

For example, if you want to specify an open drain output, I believe you place a Primitives/Buffer/opndrn symbol before the pin. There are, however, many more options that I'm having trouble finding (or guessing) in the symbols library.

What I need is a cross-reference that correlates the desired I/O function to the relative symbol in the library. Does such a cross-reference exist ?

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Hi all,

I'm relatively new to Quartus, but have used Altera and their other tools long ago. Currently, I'm using Quartus II web edition using Block/Schematic entry building a MAX II device.

A question that always comes up is: What is the active-edge/polarity of the various parts of the LEs ? Namely, the flip-flop clocks. Also, what's the polarity of the tri-state control on the IOEs ?

I guess a broader question would be, where does one find this low-level info on the specifics of the LEs ?

A 2nd Question: When specifying, for example, a device-wide output enable in the Device and Pin Options, where/how is the pin assigned?

Thanks for your help

RW

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Hi,

for detailed info's look into:

http://www.altera.com/literature/hb/max2/max2_mii51002.pdf

Kind regards

GPK