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Altera_Forum
Honored Contributor
Honored ContributorDevide in VHLD
I want to implement this function : A<= B/x"A", when I compile, the Quartus put a notice: "/" used but didn't declare. When I try with "*" (multiply) or "+" (add), it is ok. I don't know this er...
Altera_ForumHonored Contributor
Honored ContributorAll Quartus specific libraries (LPM and device specific) have been installed during initial ModelSim installation (some ModelSimDE6.1 or 6,2 version). Unlike when simulating Verilog, I don't remember missing library issues with VHDL designs. But I don't have ModelSim installed on my computer now and can't check these problems.
An additional remark related to your previously posted waveform. You didn't ever mention a device family. The timing could be explained if either belonging to a very slow logic family, or if the synthesis options in effect would allow to move an output register.
