Devide in VHLD

Alt first sight, the result_out waveform seems not to fit the above design (it may be still possible under specific conditions). result_out is a registered signal, clocked by the 100 MHz clock, but it changes shortly before the next rising edge, usually causing a setup violation for the following logic. Without knowing the previous states of all signals, and the timing constraints in effect, I can only guess about the reason for this behaviour.

I also don't understand the purpose of the strange method to do a signed multiplication. The ABS() function is by the way causing an overflow for the most negative number -32768 (0x8000), which hasn't a corresponding positive value.

P.S.: I see, that a similar negation method has been used previously in the thread. It may be a workaround for algorithms, that aren't avaliable for negative numbers for some reason. But multiply is.