Altera_Forum
Honored Contributor
15 years agoDetect Tristate 'Z' signal?!
Hello,
I have a state machine (VHDL) that should switch on an external input signal. My problem is that the input signal maybe not driven by any device, so it's value is 'Z'. How can I avoid that my state machine switches to an undefined/unintended state? It is possible to check for 'Z' values in a synthesizeable code? In RTL simulation that is not a problem but for gatelevel simulation and in the FPGA this problem could crash my design. Unfortunately, I can not change the circuit board to add a pull-up resistor to the design. Thanks for your help!