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Altera_Forum
Honored Contributor
Honored ContributorDetect Tristate 'Z' signal?!
Hello,
I have a state machine (VHDL) that should switch on an external input signal. My problem is that the input signal maybe not driven by any device, so it's value is 'Z'. How can I avoid that my state machine switches to an undefined/unintended state? It is possible to check for 'Z' values in a synthesizeable code? In RTL simulation that is not a problem but for gatelevel simulation and in the FPGA this problem could crash my design. Unfortunately, I can not change the circuit board to add a pull-up resistor to the design. Thanks for your help!6 Replies
Altera_Forumok, thanks! This solutions works :-)
- Altera_Forum
To simulate a weak pull up, you need to provide a 'H' level signal to your pin in the test bench. Then in the simulation, the signal will be 'H' when no other driver is driving the pin, and '0' or '1' when they are.
In your code, each time you read that signal, use the To_X01() function. As an example:
The function will read the value of the pin, and convert both '1' and 'H' to '1'. Then your code will have the same behaviour in the simulator and on the real chip with the pull-up. You don't need to remove the To_X01 when synthesizing, it will just be replaced by an identity function in the synthesizer.my_signal <= To_X01(my_pin); - Altera_Forum
> It is possible to check for 'Z' values in a synthesizeable code?
No. - Altera_Forum
I am not sure about Z simulation issue.
remember Z on your input is not a logic value but a case of high impedance which can go to logic 1 or zero by just touching... if input is not connected (not driven) then you can either think of it as unknown logic or being driven through air (high impedance). In similation: you define your inputs as 1 or 0 but you may try Z vector and see. Note: I have used weak pullup before in similar problem with state machine in Max II and it worked. - Altera_Forum
Ok, I think (in theorie) this should work. Fortunately MAXII CPLDs have internal pullups.
I just tried it with the internal pull-up, but my gatelevel simulation still fails?! It is possible that this weak pull-up is not simulated? In the P&R report quartus tells me that the input pin has a weak pull-up. - Altera_Forum
Good point.
set your input with weak pullup inside fpga io if availabel
