Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Detect Tristate 'Z' signal?!

Hello, I have a state machine (VHDL) that should switch on an external input signal. My problem is that the input signal maybe not driven by any device, so it's value is 'Z'. How can I avoid tha...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Ok, I think (in theorie) this should work. Fortunately MAXII CPLDs have internal pullups.

I just tried it with the internal pull-up, but my gatelevel simulation still fails?! It is possible that this weak pull-up is not simulated? In the P&R report quartus tells me that the input pin has a weak pull-up.