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Altera_Forum
Honored Contributor
Honored ContributorDetect Tristate 'Z' signal?!
Hello, I have a state machine (VHDL) that should switch on an external input signal. My problem is that the input signal maybe not driven by any device, so it's value is 'Z'. How can I avoid tha...
Altera_ForumHonored Contributor
Honored ContributorGood point.
set your input with weak pullup inside fpga io if availabel
