New ContributorHello all,
I am looking for the right primitive to act as a strong buffer for combinatorial logic block. The driven output of a NAND gate will be the input of many gates. In theory a logical-effort calculation can be done resulting in a buffer chain - the thing is I could not find any buffer other than LCELL (which comes with only a single size).
Would appreciate any thoughts,
Tom
Regular ContributorHi Tom,
You can use this buffer IP here: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altiobuf.pdf
Let me know if you have more questions.
Regards,
Nurina
New ContributorHello,
Thanks for the quick reply. From my understanding these buffers are located near the GPIO pins and their are only a few of these (couldn't find the exact number), am I correct?
Can I use this IP to drive internal logic?
Thanks,
Tom
Regular ContributorHi Tom,
I see your problem now, here's a reference of buffer primitives you can use: https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/mapIdTopics/jka1465579929642.htm
You should be aware that some of these buffer primitives aren't supported by the newer version of Quartus and Cyclone V devices, so you don't have much choices unfortunately.
You can refer to this document on how to use the buffer primitives: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_low_level.pdf
Best regards,
Nurina
Regular ContributorHi Tom,
We did not receive any response to the previous answer that I have provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.
Regards,
Nurina
PS: If you find any comment from the community or Intel Support to be helpful, feel free to give Kudos.
