Forum Discussion
supermant
New Contributor
New ContributorDesign with multiple PMA/PCS cores
Hi,
I am trying to have a design which is connected as shown in the image.
As per my understanding the 4 PHY(PMA/PCS) blocks would typically be in 4 different clock domains. What would be the be...
Ash_R_Altera
Regular Contributor
Regular ContributorHi,
Usually every transceiver block has its own clocking structure which includes a PLL. Please check the corresponding transceiver user guide for more details.
In devices like Stratix 10 and below, you can also use the transceiver PLL generated clock for the FPGA fabric design as well.
Regards
