Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributordesign Optimization
Hi,
I am working on a design done by one of the team member. I would like to bring the utilization to 85%, below is the project summary, whats the best way to reduce the design for future addition: design summary Number of registers: 1330 PFU registers: 1318 PIO registers: 12 Number of SLICEs: 1025 out of 1056 (97%) SLICEs(logic/ROM): 264 out of 264 (100%) SLICEs(logic/ROM/RAM): 761 out of 792 (96%) As RAM: 33 out of 792 (4%) As Logic/ROM: 728 out of 792 (92%) Number of logic LUT4s: 1275 Number of distributed RAM: 33 (66 LUT4s) Number of ripple logic: 344 (688 LUT4s) Number of shift registers: 0 Total number of LUT4s: 2029 Number of PIO sites used: 33 out of 105 (31%) Number of block RAMs: 6 out of 8 (75%) Number of GSRs: 1 out of 1 (100%) EFB used : Yes JTAG used : No Readback used : No Oscillator used : Yes Thanks for your help in advance.4 Replies
Altera_ForumIt is difficult to answer this question on a generic level. It depends a lot on the system design. In the Tools menu you have a "Resource Optimization Advisor" that can give you a few ideas.
That said, the terms "PFU" and "SLICE" seem to indicate that you aren't using Altera tools.- Altera_Forum
This sounds more like a Xilinx report.
- Altera_Forum
Hi,
I am using Lattice tools. Other than optimizing the design for area option I dont see anywhere in tool settings that can optimize this design. The only way I feel I can reduce the logic is to have simpler verilog code. Is there any other way? Thanks - Altera_Forum
Lattice are a competitor to Altera, so I suggest you contact them about specific tool related questions.
But usually resource usage is down to source code. you may want to see which modules are using the most and see what you can do to optimise.
