Altera_Forum
Honored Contributor
13 years agodesign Optimization
Hi,
I am working on a design done by one of the team member. I would like to bring the utilization to 85%, below is the project summary, whats the best way to reduce the design for future addition: design summary Number of registers: 1330 PFU registers: 1318 PIO registers: 12 Number of SLICEs: 1025 out of 1056 (97%) SLICEs(logic/ROM): 264 out of 264 (100%) SLICEs(logic/ROM/RAM): 761 out of 792 (96%) As RAM: 33 out of 792 (4%) As Logic/ROM: 728 out of 792 (92%) Number of logic LUT4s: 1275 Number of distributed RAM: 33 (66 LUT4s) Number of ripple logic: 344 (688 LUT4s) Number of shift registers: 0 Total number of LUT4s: 2029 Number of PIO sites used: 33 out of 105 (31%) Number of block RAMs: 6 out of 8 (75%) Number of GSRs: 1 out of 1 (100%) EFB used : Yes JTAG used : No Readback used : No Oscillator used : Yes Thanks for your help in advance.