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Altera_Forum
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18 years ago

Design no longer compiles. IEEE-1532 error

Don't know what I did, but my design no longer compiles if I use MAX7000S family. Error message says:

"Device or configuration device EPM7064DT44 not IEEE-1532 compliant."

Some other families compile, others have errors that say TTL not supported.

Where is the button that selects TTL on or off? Not that I want that.

The design was previously working.

7 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    I don't know if this is the cause, but I was trying to assign the clock.

    When it was working, the assignment editor said I used 24 pins, now it says 25 pins are used, and two of them are clocks.
  • Altera_Forum's avatar
    Altera_Forum
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    ok, copied my schematic to clipboard, then opened a new project and pasted the schematic into a new schematic file.

    Compiles, running simulator. ok, design works, but click "View" then "Show Pin and Location Assignments", nothing happens, no pins are assigned.

    How to make it automatically assign pins? Then go back and change them so the layout is easy? I think that's how I got messed up before.
  • Altera_Forum's avatar
    Altera_Forum
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    Ha! Changed some settings in the Device and Pin options, compile failed again. It gives the IEEE 1532 error if I select "In System Configuration File", but no error if I select "Serial Vector Format".

    Isn't it fun watching a newbie stumble in the dark?
  • Altera_Forum's avatar
    Altera_Forum
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    --- Quote Start ---

    How to make it automatically assign pins? Then go back and change them so the layout is easy?

    --- Quote End ---

    If the target device you select is"Specific device selected in'Avaliable devices' list then

    you shoule assign pins

    else

    no need;

    end if;

    A Quartus_hand book may help, try it.

    Good luck.
  • Altera_Forum's avatar
    Altera_Forum
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    I used the tutorial, and did Processing->Start->Start Analysis and Synthesis. then Start Fitter.

    View->Timing Closure Floorplan shows pins assigned.

    Design has ripple clock warnings. Keep working. 60/64 cells used, might have to use bigger device.

    See new thread.
  • Altera_Forum's avatar
    Altera_Forum
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    Thanks, my search found that. I fixed one of the warnings.

    For the other warnings I tried using a DFF with enable but it made the design blow up. Negative set up times everywhere, simulation waveforms were buzzing.