Forum Discussion
FBels
New Contributor
New ContributorDesign migration question, Cyclone to Max10, gpio lite related
I am converting a Verilog design from Cyclone IV to Max10.
I noticed that the original Cyclone IV Quartus gpio lite Verilog code for a bidir includes text about the intended chip being a Cyclone ...
FBelsNew Contributor
New ContributorThe document link you provided is for Max V, not Max 10, and furthermore ends at page 39.
AminT_Intel
Regular Contributor
Regular ContributorHello,
Thank you for pointing that out! The correct link is https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_gpio.pdf
The rest of the page reference is the same as my previous post.
