Forum Discussion

FBels's avatar
FBels
Icon for New Contributor rankNew Contributor
5 years ago

Design migration question, Cyclone to Max10, gpio lite related

I am converting a Verilog design from Cyclone IV to Max10. I noticed that the original Cyclone IV Quartus gpio lite Verilog code for a bidir includes text about the intended chip being a Cyclone ...
AminT_Intel's avatar
AminT_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hello,

The function does not need to be regenerated from Cyclone device to Max 10. I would advise you to double-check on bidir transition, and always verify the pin migration compatibility through Pin Migration View check Migration Capability on your Intel FPGA device like in page 5 from this link: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-v/mv51003.pdf

There is detailed information about Verifying Pin Migration Compatibility on page 44

There is more information about GPIO Lite of Max 10 in page 41 of the same document.

I hope this answer helps.

FBels's avatar
FBels
Icon for New Contributor rankNew Contributor
5 years ago

The document link you provided is for Max V, not Max 10, and furthermore ends at page 39.