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Altera_Forum's avatar
Altera_Forum
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11 years ago

Design example transceiver Cyclone V GT

Hi,

I would like to debugging a cyclone V Gt board with transceiver toolkit examples.

I work with Quartus II V13.1.4 Build 182.

I taked here :

http://www.altera.com/support/examples/on-chip-debugging/on-chip-debugging.html?gsa_pos=2&wt.oss_r=1&wt.oss=cyclone%20v%20gt%20transceiver

"transceiver toolkit examples for stratix® v gx, arria v gx/gt, cyclone v gx/gt and stratix iv gx/gt devices (http://www.altera.com/support/examples/download/transceiver_toolkit_13_0sp1_qar.zip) (quartus ii software v13.0 sp1)

with quartus ii software version 13.0 sp1, there are new examples for stratix v gx, arria v gx/gt, cyclone v gx/gt and stratix iv gx/gt. these examples must be used with quartus ii software version 13.0 sp1 or later."

It works for one lane but when i try to modify the Qsys for two (or more) lanes i have these errors on Analysis and Synthesis :

error: hssi pma tx buffer node 'gx_link_test_system:u2|altera_xcvr_custom:xcvr_custom_phy_0|av_xcvr_custom_nr:a5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[1].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_tx_pma:av_tx_pma|av_tx_pma_ch:tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_pma_buf.tx_pma_buf' is not properly connected on the 'dataout' port. it must be connected to one of the valid ports listed below.

info: can be connected to i port of arriav_io_obuf wysiwyg

error: hssi pma tx buffer node 'gx_link_test_system:u2|altera_xcvr_custom:xcvr_custom_phy_0|av_xcvr_custom_nr:a5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_tx_pma:av_tx_pma|av_tx_pma_ch:tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_pma_buf.tx_pma_buf' is not properly connected on the 'dataout' port. it must be connected to one of the valid ports listed below.

info: can be connected to i port of arriav_io_obuf wysiwyg

error: hssi pma tx buffer node 'gx_link_test_system:u2|altera_xcvr_custom:xcvr_custom_phy_0|av_xcvr_custom_nr:a5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[1].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_tx_pma:av_tx_pma|av_tx_pma_ch:tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_pma_buf.tx_pma_buf' is not properly connected on the 'dataout' port. it must be connected to one of the valid ports listed below.

info: can be connected to i port of arriav_io_obuf wysiwyg

error: hssi pma tx buffer node 'gx_link_test_system:u2|altera_xcvr_custom:xcvr_custom_phy_0|av_xcvr_custom_nr:a5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_tx_pma:av_tx_pma|av_tx_pma_ch:tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_pma_buf.tx_pma_buf' is not properly connected on the 'dataout' port. it must be connected to one of the valid ports listed below.

info: can be connected to i port of arriav_io_obuf wysiwyg

I don't know why the IP uses some Arria V submodules. This IP doesn't exist in QSYS Library for Cyclone V Gt.

Somebody already try with several lanes ?

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Hi reflex,

    very basic question, but did you regenerated the qsys project after you changed the lanes to 4?

    Kr,

    Florian
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Hi,

    It's impossible to instantiate four times the QSYS block because you have to use the same reconfig block within the same transceiver block. We must change the QSYS to multiply the different IP (pattern generator, adapator timing pattern checker etc).

    I did regeneration and I have theses errors on analysis and synthesis. I tried several version of Quartus II (12.1 SP1, 13.1.4, 14.0), i tried to delete et regenerate the IP custom_phy..
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Hi,

    By looking at the error messages, it seems to relate to the XCVR serial input and output pins are not properly connected at the top level. Note that the XCVR pins must be exported from the Qsys and directly connected to XCVR pins in the design.

    By the way, I understand that there is a 4 lane design example for SV device. Probably you could try to refer to it to see if can find any clue with your error.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    It seems like user did not connect the physical XCVR pins at the pin planner/assignment editor.