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Altera_Forum's avatar
Altera_Forum
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11 years ago

Design Environment (Desktop Performance)

FPGA is Big Enough, but the simulation takes too long. When we try to design with the actual target board, the timing simulation might take pretty long time with bigger logics. Recently, I wa...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Most big FPGA designs don't do timing simulations anymore for this reason. RTL simulations and static timing analysis(TimeQuest) should cover everything.