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Altera_Forum
Honored Contributor
Honored ContributorDesign Environment (Desktop Performance)
FPGA is Big Enough, but the simulation takes too long. When we try to design with the actual target board, the timing simulation might take pretty long time with bigger logics. Recently, I wa...
Altera_ForumHonored Contributor
Honored ContributorMost big FPGA designs don't do timing simulations anymore for this reason. RTL simulations and static timing analysis(TimeQuest) should cover everything.
