Forum Discussion
Occasional ContributorDeserializers in Agilex 3 series
Hi,
Agilex 3 lvds serdes only has x4 and x8 serdes factor. If you check datasheet and i screenshot the ip settings as below (had been confirmed among lvds team):
How does Altera suggest a 360Mhz, x10 bit deserialization factor, 5-Lane SerDes be implemented in the Agilex 3 device?
Do it with an x8 deserializer. Deserialize each lane by 8. Line rate = 360 MHz × 10 = 3.6 Gb/s (SDR). Line rate = 360 MHz × 10 = 3.6 Gb/s (SDR). Parallel rate after ÷8 = 3.6 Gb/s ÷ 8 = 450 MHz byte (8-bit) clock/domain. Feed the 360 MHz source-synchronous clock into an IOPLL and outputs with 360 MHz = your final 10-bit symbol clock (core domain) while 450 MHz = the x8 parallel domain for the SERDES output. Ratio is 450/360 = 1.25 (fractional PLL). Keep both clocks phase-related.
We have clock crossing adapter type to adapt the CDC https://www.intel.com/content/www/us/en/docs/programmable/683364/18-1/interconnect-requirements.html
Super ContributorHi,
The Agilex 3 lvds serdes factor had been confirmed support 4 and 8 only. So if port the altlvds rx ip to Agilex 3, can only use 4 and 8.
UMall1I thought the Deserialization factor can span a number between x4 - x8 - as seen in the image below (Taken form theAgilex3 datasheet).
How does Altera suggest a 360Mhz, x10 bit deserialization factor, 5-Lane SerDes be implemented in the Agilex 3 device? I do not think I am reaching the right people for support. Can someone forward the request to someone who specializes in SerDes circuits in the Agilex 3 device.
UM
