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Altera_Forum
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16 years ago

Deserialize LVDS channels coming from different banks (TOP and RIGHT edges)

Hello all: I'm designing an interface receiving 28 LVDS channels (plus a clock) that are deserialized in a FPGA. I would like to use EP3C16F484 pin compatible with EP3C40F484. I have plenty of ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Thanks for your quick reply. I'm checkin if the fmax with such configuration is ok for me. If not I will have to select one FPGA instead of using the pin compatible version.