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Altera_Forum's avatar
Altera_Forum
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15 years ago

Deserialize LVDS channels coming from different banks (TOP and RIGHT edges)

Hello all:

I'm designing an interface receiving 28 LVDS channels (plus a clock) that are deserialized in a FPGA. I would like to use EP3C16F484 pin compatible with EP3C40F484. I have plenty of LVDS channnels in bank 7 and 8 (TOP) to hold such signals (28 + clock) but when making both FPGAs pin compatible some channels are not shared and therefore lost. So I need to use some LVDS channels from bank 6 (RIGHT).

The question is wether it is possible to feed a FPGA LVDS deserializer with signals from TOP and RIGHT banks. When compiling the design the folllowing warning shows up:

Warning: Input pins that are compensated by the source-synchronous PLL "altlvds_rx_serdes:inst|altlvds_rx:altlvds_rx_component|lvds_rx_ubr1:auto_generated|lvds_rx_pll" are spread accross multiple edges

Info: Input pin "lvds_data[27]" is on the top edge

Info: Input pin "lvds_data[26]" is on the top edge

Info: Input pin "lvds_data[25]" is on the top edge

Info: Input pin "lvds_data[24]" is on the top edge

Info: Input pin "lvds_data[23]" is on the top edge

Info: Input pin "lvds_data[22]" is on the top edge

Info: Input pin "lvds_data[21]" is on the right edge

Info: Input pin "lvds_data[20]" is on the top edge

Info: Input pin "lvds_data[19]" is on the top edge

Info: Input pin "lvds_data[18]" is on the top edge

...

...

Thanks,

Luis

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi Luis,

    I think it is possible to use different edges for your serdes. But your lvds speed will be limited, because of the differences in path delays. Now you are using the internal PLL in source-synchronous mode. Maybe for your application it's better to use an external PLL in normal mode. And then tune the PLL phase to optimum for both top and right signals.

    Another idea could be to feed the clock to both top edge and right edge and also use a separate serdes for your top and right signals, combining the serdes outputs afterwards. A bit tricky, I must admitt, but not impossible.

    But whatever you do: Don't use odd deserialisation factors.

    Good luck, Ton
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Thanks for your quick reply. I'm checkin if the fmax with such configuration is ok for me. If not I will have to select one FPGA instead of using the pin compatible version.