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Altera_Forum
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16 years ago

Deserialize LVDS channels coming from different banks (TOP and RIGHT edges)

Hello all: I'm designing an interface receiving 28 LVDS channels (plus a clock) that are deserialized in a FPGA. I would like to use EP3C16F484 pin compatible with EP3C40F484. I have plenty of ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Hi Luis,

I think it is possible to use different edges for your serdes. But your lvds speed will be limited, because of the differences in path delays. Now you are using the internal PLL in source-synchronous mode. Maybe for your application it's better to use an external PLL in normal mode. And then tune the PLL phase to optimum for both top and right signals.

Another idea could be to feed the clock to both top edge and right edge and also use a separate serdes for your top and right signals, combining the serdes outputs afterwards. A bit tricky, I must admitt, but not impossible.

But whatever you do: Don't use odd deserialisation factors.

Good luck, Ton