derived clock versus clock enable

OK - so I tried your suggestion and it did pretty much as you said. However, something is still bothering me.

My test design does the following:

-clk25 driving a PLL

-PLL multiplies x 6 to form clk150

-counter divides 150 by 19 to make clk8 (7.8 is closer to 8 than 8.3)

-add clock setting for clk25

-add derived clock setting for clk8 (*6/19, phase unspecified)

-do sequential logic within clk8 domain

-include a sequential path launched by a register in the clk150 domain and latched by another in the clk8 domain

To my wonder and amazement, the timing analyzer figured all this out and I ended up with no warnings or errors.

What is bothering me is that the offset between clk150 and clk8 calculated by the TA was 4 nsec. which I'm thinking must be the worst-case delay between clk150 and the divider bit acting as clk8. The cross-domain path passed because 4 nsec. was enough setup time for the path. But the 4 nsec. could certainly be a lot less and probably would be under normal conditions of PVT. So what would really be needed here for a valid solution is to have the timing analyzer consider the smallest possible delay between clk150 and clk8 edges because the cross-domain path must sneak into this slot.

Does this make any sense?

Bruce