derived clock versus clock enable

With a PLL, you usually do not need to create a clock setting for the PLL input or any outputs because those are created automatically by the Classic Timing Analyzer. It's OK though to assign a clock setting to the device pin for the clock input to the PLL. (Don't assign a clock setting to a PLL output. That wasn't supported by past Quartus versions and could cause nonobvious problems. I doubt that support for it has been added.) You can assign a 25 MHz absolute clock setting to the clock input pin to match the PLL MegaWizard setting and create a derived-clock setting that divides by 3 for assignment to the 8.3 MHz clock node. Quartus will account for the PLL when analyzing synchronous cross-domain paths.

But as I said before, it's ok to use an absolute clock setting of 8.3 MHz on the divided-down clock if you have no synchronous cross-domain paths. If you use an absolute 8.3 MHz clock setting, you don't need a clock setting for the 25 MHz PLL input as a reference for the 8.3 MHz clock setting.