derived clock versus clock enable

I have a similar problem. I apologize in advance if the answer is in a previous post, but I'm kinda new at this game so I might not have recognized it. Here's my problem:

-I'm using Quartus 7.1 with Classic Timing Analyzer for a Stratix II design.

-I have a 150 MHz. clock which is divided by a simple f/18 state machine yielding an 8.3 MHz. derived clock

-I have a collection of logic being clocked by the 8.3 MHz. derived clock, with no synchronous data paths into or out.

-The timing analyzer is reporting setup violations based on the assumption that the available setup time is 6.667 nsec., while in fact the allowable setup time withing this slow clock domain is 18 times that.

-Based on the previous posts, I would be wise to eliminate the derived clock, but assume I can't and must deal with it.

I'm thinking I can fix this with a simple multicycle assignment, but I can't for the life of me figure out how. Can somebody please suggest the proper form of the multicycle assignment that will fix this problem?

Thanks,

Bruce