derived clock versus clock enable

@Epis:

See page 6-34 at Quartus II Version 7.1 Handbook or search for "multicycle" in this PDF.

@Brad:

Thank you for your answer.

I am still wondering about the create generated clock sdc constraint.

Am I wrong if I say this:

I have a divided clock clk_div. I constrain it correctly with TimeQuest. I provide clk_div to the fast global clock network.

1) My Desing will be faster than the clock enable version because I don't have the delay of the (very) high fanout of the clock enable signal, which can slow down the design (can it?).

2) My Design is reliable.

(When not for what do I need the generated clock constraint)

Can you suggest good literature for this problem?

Best regards,

Axel